Microwave Heating for Semiconductor Nanostructure Fabrication

ABSTRACT

The present invention grows nanostructures using a microwave heating-based sublimation-sandwich SiC polytype growth method comprising: creating a sandwich cell by placing a source wafer parallel to a substrate wafer, leaving a small gap between the source wafer and the substrate wafer; placing a microwave heating head around the sandwich cell to selectively heat the source wafer to a source wafer temperature and the substrate wafer to a substrate wafer temperature; creating a temperature gradient between the source wafer temperature and the substrate wafer temperature; sublimating Si- and C-containing species from the source wafer, producing Si- and C-containing vapor species; converting the Si- and C-containing vapor species into liquid metallic alloy nanodroplets by allowing the metalized substrate wafer to absorb the Si- and C-containing vapor species; and growing nanostructures on the substrate wafer once the alloy droplets reach a saturation point for SiC. The substrate wafer may be coated with a thin metallic film, metal nanoparticles, and/or a catalyst.

CROSS REFERENCE TO RELATED APPLICATIONS

The present application claims the benefit of provisional patentapplication Ser. No. 61/051,902 to Sundaresan et al., filed on May 9,2008, entitled “Nanowire Growth Using Microwave Heating-AssistedPhysical Vapor Transport,” which is hereby incorporated by reference.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

This invention was made with government support under grantW911NF-04-1-0428 awarded by the Army Research Office; SBIR grant no.0539321 awarded by National Science Foundation (NSF); grant no. DMR05-20471 awarded by NSF UMD MRSEC; and award nos. ECS-0618948 andECCS-0742139 both awarded by NSF. The government has certain rights inthe invention.

BACKGROUND OF THE INVENTION

Over the past decade, one dimensional (1D) semiconductor nanostructures,such as nanotubes and nanowires, have attracted special attention due totheir high aspect and surface to volume ratios, small radius of theirtips, absence of three dimensional (3D) growth related defects, such asthreading dislocations, and fundamentally new electronic propertiesresulting from quantum confinement. These nanostructures can be used asbuilding blocks for future nanoscale electronic devices andnanoelectromechanical systems (NEMS), designed using a bottom-upapproach. A variety of 1D nanowires of Si, ZnO, SiC and othersemiconductors have been synthesized.

Taking SiC as an example, SiC offers opportunities in fabricatingnanoelectronic devices and NEMS for chemical/biochemical sensing,high-temperature, high-frequency and aggressive environmentapplications. These opportunities are due to wide bandgap, high electricbreakdown field, mechanical robust, chemical inertness andbiocompatibility.

However, before any of the above-mentioned applications could berealized, a reliable technique for the high yield, cost effectivefabrication of SiC nanostructures with controlled morphology (size,shape, location, and orientation), structure (polytype and defects) andelectronic properties (doping level and transport) needs to bedeveloped. Currently, post-growth processing and manipulation ofnanostructures is an extremely difficult task.

Several known techniques have been applied to synthesize SiC nanowiresusing physical evaporation, chemical vapor deposition, laser ablation,direct chemical reaction, etc. However, such existing growth methods forsynthesis of SiC nanostructures exhibit several problems andlimitations. First, all of the existing methods can grow only 3C—SiCpolytype nanowires, while methods for selective growth of otherpolytype, such as hexagonal 4H and 6H—SiC nanowires, have not yet beendeveloped. It is known that the hexagonal SiC polytypes have manyadvantageous properties over 3C—SiC, such as larger bandgap, lowerintrinsic carrier concentration, higher hole mobility and higherbreakdown voltage, etc. The lack of the ability to fabricate hexagonalSiC polytype nanowires is a significant draw back for the use of SiCnanowires in many important applications.

Second, the growth of SiC nanostructures using the above-mentionedconventional methods is very slow (in the μm range per hour), and themorphology of the SiC nanostructures are uncontrollable. Different sizesand shapes of nanostructures, such as nanowires, nanoribbons, nanosawsand two dimensional (2D) or 3D features, are often present in the samesample. Consequently, the 1D nanostructures with desired morphologiesand properties constitute just a fraction of the total yield. The slowgrowth rate and low yield of desired nanostructures become criticaltechnical barriers for the practical applications of the existing growthmethods in terms of large quantity and low-cost fabrication of SiCnanostructures.

Consequently, what is needed is a simpler and more effective techniqueto overcome the above mentioned technical barriers in order to open thedoors for high-yield, cost-effective growth of nanowires (e.g., SiCnanowires, etc.) with selected polytype, morphology, and properties.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a flow diagram of a microwave-based sublimation-sandwichSiC nanostructure growth method as per one aspect of the presentinvention.

FIG. 2 shows an example of a block diagram of a solid-state microwaveannealing system.

FIG. 3 shows another example of a block diagram of a solid-statemicrowave annealing system.

FIG. 4 shows an example of a typical heating cycle, where the sample is4H—SiC, the applied microwave power is 104 W, and the steady statetemperature is ˜1800° C. and maintained for about 15 s.

FIG. 5 shows a schematic example of the “sublimation-sandwich” cell usedto grow SiC nanowires.

FIG. 6 shows an example of an FESEM image of SiC nanowires grown atT_(s)=1700° C. and ΔT=150° C. for 40 s.

FIG. 7 shows an example of statistical distribution of the SiC nanowirediameters, where about 42% of the nanowires have diameters≦100 nm.

FIG. 8 shows an examples of (a) cone-shaped SiC nanostructures grown atT_(s)=1600° C. and ΔT=150° C., and (b) needle-shaped SiC nanostructuresgrown at T_(s)=1700° C. and ΔT=250° C.

FIG. 9 shows an example of a typical x-ray diffraction spectrum obtainedfrom the SiC nanowires grown.

FIG. 10 shows examples of (a) FESEM image of a SiC nanowire harvested ona heavily doped Si substrate, (b) EBSD pattern from the nanowire indexedto the 3C—SiC phase, and (c) EBSD pattern from the nanowire tip indexedto Fe₂Si.

FIG. 11 shows examples of diffraction contrast TEM images of two typesof 3C—SiC nanowires, with (a) being twin-like defects are observed ondifferent sets of {111} planes, and (b) being high-incidence of planardefects parallel to {111} planes along the wire axis.

FIG. 12 shows an example of μ-Raman spectrum from an isolated SiCnanowire.

DETAILED DESCRIPTION OF THE INVENTION

The present invention embodies novel microwave heating techniques fordeveloping high yield, controlled growth of nanostructures with welldefined morphology, polytypes and properties. In one embodiment, thepresent invention embodies the growth of silicon carbide (SiC)nanostructures.

Referring to FIG. 1, a microwave-based sublimation-sandwich SiC polytypegrowth method is shown. Carried out in a modified solid-state microwave(SSM) system (as described herein), the method comprises the following.One, a sandwich cell is created by placing a source wafer parallel to asubstrate wafer, leaving a small gap between the source wafer and thesubstrate wafer S105. Two, a microwave heating head is placed around thesandwich cell to selectively heat the source wafer to a source wafertemperature and the substrate wafer to a substrate wafer temperatureS110. Three, a temperature gradient between the source wafer temperatureand the substrate wafer temperature is created S115. Four, silicon (Si-)and carbon (C-) containing species sublimate from the source wafer,producing Si- and C-containing vapor species S120. Five, the Si- andC-containing vapor species are converted into liquid metallic alloydroplets (which may be nanodroplets) by allowing the substrate wafer toabsorb the Si- and C-containing vapor species S125. Six, nanostructuresare grown on the substrate wafer once the alloys reach a saturationpoint for SiC S130.

In another embodiment, the present invention similarly discloses asublimation-sandwich SiC polytype growth method. This method comprises(a) creating a sandwich cell by placing a source wafer parallel to asubstrate wafer, leaving a small gap between the source wafer and thesubstrate wafer; (b) placing a heating unit around the sandwich cell toselectively heat the source wafer to a source wafer temperature and thesubstrate wafer to a substrate wafer temperature; (c) creating atemperature gradient between the source wafer temperature and thesubstrate wafer temperature; (d) sublimating silicon (Si-) and carbon(C-) containing species from the source wafer, producing Si- andC-containing vapor species; (e) converting the Si- and C-containingvapor species into liquid droplets of metal-ion alloys by allowing thesubstrate wafer to absorb the Si- and C-containing vapor species; and(f) growing nanostructures on the substrate wafer once the alloys reacha saturation point for SiC.

For each of these methods, the following embodiments apply to thepresent invention.

The SiC polytype can be hexagonal SiC (e.g., 4H—SiC, 6H—SiC, etc.) or acubic SiC (e.g., 3H—SiC), or any other type. The source wafer may be ann-type or p-type doped SiC.

The substrate wafer may be a semi-insulating SiC. Alternatively, thesubstrate wafer may be an at least one order less doped SiC, as comparedto the source wafer. For instance, if the source wafer is doped to 10¹⁹dopant atoms/cm³, then the substrate wafer is doped to less than orabout equal to 10¹⁸ dopant atoms/cm³. The small gap between the waferscan be at least about 0.3 mm. It should be noted that polytype growthmeans growing one or more different polytypes.

N-type (where “n” means negative) and p-type (where “p” means positive)are terms generally associated with doping of semiconductors. Doping iscommonly known as a process of intentionally introducing trace amountsof one or more elements (namely, one or more impurities) to a puresemiconductor to alter the electrical properties of the semiconductor.For n-type doping, there needs to be at least one unbounded valenceelectron in the semiconductor. For p-type doping, there needs to be atleast one covalent bond being deficient in electrons.

Take silicon as a semiconductor example. Silicon has four valenceelectrons, which are used to form covalent bonds to other atoms. Tocreate n-type doping, an impurity (an element) having five or morevalence electrons (e.g., a Group VA element, such as arsenic) may beadded to the silicon. When covalent bonds are formed with the impurity,there will be at least one valence electron that does not form acovalent bond. The extra electron(s) creates a negative charge as itmoves through the solid under an applied voltage.

To create p-type doping, an impurity having three or less valenceelectrons (e.g., a Group IIIA element, such as boron (B)) may be addedto the silicon. For each impurity added, at least one of the covalentbonds from the silicon will be deficient in electrons because it hasless than four valence electrons. When covalent bonds are formed withthe impurity, one or more electrons from a neighboring atom can moveover to fill this deficiency, leaving a positive “hole” behind. Suchhole can be filled by another electron from another atom. However, theeffect of that migration still results in another hole. As such, underapplied voltage, the missing electron(s) create a positive charge.

The inner surface of the substrate wafer is coated with a catalyst. Suchcoating creates a catalyst layer. The catalyst may be a metal catalyst.Nonlimiting examples of metal catalysts include iron (Fe), nickel (Ni),palladium (Pd), platinum (Pt), etc. The catalyst layer may be apatterned layer. For instance, the catalysts may be placed in acheckerboard pattern, circular pattern, rectangular or other polygonalpattern, linear pattern, etc. Catalysts may also be placed randomly.

The sandwich cell and the microwave heating head may be placed in avacuum chamber. Alternatively, they may be placed in a dopant gasatmosphere. A dopant gas includes nitrogen, borine, phosphine, etc., orit can be any gas having a dopant as a constituent element.

It should be noted that throughout the present invention, one or moremicrowave heating heads can be used. The mere mentioning of the term“microwave heating head” in the singular sense does not mean that thepresent invention is limited to using only one microwave heating head.

In addition to the microwave heating head, which is known in the art,the present invention can also use any other known heating unit. Forexample, the heating unit may be a laser annealing system (such as LA-TFor Laser Anneal 6300, both by AMBP Tech of Piscataway, N.J.). In yetanother example, the heating unit may be a halogen or mercury lamp.

While these heating units are known, the present invention's doped GaNannealing techniques remain novel. It is within the scope of the presentinvention that such annealing techniques include, but is not limited to,microwave heating annealing, laser annealing, halogen lamp annealing,mercury lamp annealing, etc. Although the following embodiments usemicrowave heating annealing as an example, any of these exemplifiedtechniques may be used to achieve the requisite high heating rates andtemperatures of the present invention.

The method may further include controlling the morphology of thenanostructures by varying the substrate wafer temperature and thetemperature gradient. Morphology refers to shape, size, and/or location.Nanostructures refer to a type of structure that is nano-sized. Forinstance, the morphological shape (structure) of a nanostructure can bea nanowire, nanocone, nanorod, nanoneedle, 2D nanostructure, 3Dnanostructure, etc.

Additionally, the method may include controlling the SiC polytype growthby varying the substrate wafer temperature and polarity of the substratewafer. The polarity may be either Si-face or C-face. Moreover, themethod may include controlling the SiC polytype growth by varying vaporphase composition. The vapor phase composition may include an Si/C molarratio in ambient and at least one impurity.

In yet another embodiment, the present invention further includescontrolling the morphology of the nanostructures by selecting a sourcewafer with at least one dopant. Nonlimiting examples of the dopantinclude aluminum, nitrogen, etc.

The substrate wafer temperature should be greater than or about equal tothe melting point of the catalyst, and the temperature gradient may beat least about 100° C. Furthermore, a heating rate should be at leastabout 100° C./s and a cooling rate should be at least about 100° C./s.Having a high heating rate and cooling rate is beneficial for the fastgrowth and high yield of nanostructures (e.g., nanowires, nanocones,nanorods, nanoneedles, etc.).

The saturation point refers to the maximum amount of Si and C that thesubstrate wafer can absorb after the catalyst melts. This absorption isdependent upon the temperature of the liquid droplets of the metal-ionalloys. These metal-ion alloys may be formed by combining ions from thecatalyst, the SiC polytype, and/or the substrate wafer.

I. INTRODUCTION

SiC belongs to a class of semiconductors known as wide band-gapsemiconductors. SiC is a wide band gap semiconductor that possesses highthermal conductivity, high breakdown electric field, and chemical andmechanical stability. Because of these properties, SiC devices canperform under high-temperature, high-power, and/or high-radiationconditions in which conventional (e.g., narrow band gap) semiconductorscannot adequately perform. The ability of SiC to function under extremeconditions is expected to enable significant improvements to a farranging variety of applications and systems. SiC power devices haveimproved high-voltage switching characteristics compared withconventional semiconductors, such as like Si and GaAs. Applications ofhigh-power SiC devices range from public electric power distribution andelectric vehicles to more powerful SSM sources for radar andcommunications to sensors and controls for cleaner-burning, morefuel-efficient, jet aircraft and automobile engines.

SiC offers opportunities in fabricating nanoelectric devices and NEMSfor chemical/biochemical sensing, as well as high-temperature, highfrequency, and/or aggressive environment applications. Theseopportunities may be due to wide bandgap, high electric breakdown field,mechanical robustness, chemical inertness, and/or biocompatibility.

As indicated in the following table, TABLE 1 shows a comparison ofmaterial properties of several semiconductors, namely Si, GaAs, and SiC.

TABLE 1 Material Properties of Semiconductors Si, GaAs, and SiCAttribute Si GaAs 4H—SiC Energy Gap (eV) 1.11 1.43 3.2 Breakdown E-Field(V/cm) 6.0 × 10⁵ 6.5 × 10⁵ 3.5 × 10⁶ Saturation Velocity (cm/s) 1.0 ×10⁷ 2.0 × 10⁷ 2.0 × 10⁷ Electron Mobility (cm²/V-s) 1350 6000 800Thermal Conductivity (W/cmK) 1.5 0.46 3.5 Heterostructures SiGe/SiAlGaAs/GaAs None InGaP/GaAs AlGaAs/ InGaAs

An example of a SSM RTP system 201 used in this work is illustrated inFIG. 2 and FIG. 3. This SSM RTP system has three main building blocks:(1) a variable frequency microwave solid state power source 205, whichconsists of a signal generator 210 and a power amplifier 215, (2) amicrowave heating system 220, which consists of a coupling and tuningcircuit 225 and at least one microwave heating head 230, 315, forcoupling microwave power to the targeted source wafer having a T1 305and (3) a measurement and control system 235, which consists of anetwork analyzer 240, a computer 245, an optical pyrometer 250, andother equipment. Below the targeted source wafer having a T1 305 andseparated by a small gap is the substrate wafer having a T2 310. Thetemperature difference between T1 and T2 forms the temperature gradientΔT. Microwave power generated by the variable frequency power source 205is amplified and then coupled to a SiC sample 255, 310 through themicrowave heating head 230. The environmental gas and pressure of thechamber can be controlled by vacuum pump 325 and external vapor/gassource 320. The sample temperature can be monitored through a viewport330 by an infrared pyrometer or the optical pyrometer 250. The SiCsample emissivities can be measured using a blackbody source. Themeasured emissivity value (e.g., 0.8) is then keyed into the pyrometerfor all temperature measurements.

The microwave system 315 above can be tuned to efficiently heatsemiconductor samples at variable frequencies. For instance, operatingat about 150 W, the frequency may range from about 910 MHz to about 930MHz. A typical temperature/time cycle of this system for heating 5 mm×5mm heavily (in-situ) doped 4H—SiC is shown in FIG. 4. In this figure,the sample used was 4H—SiC. The applied microwave power was 104 W. Thesteady state temperature of ˜1800° C. was maintained for about 15seconds.

Since samples should be placed in an enclosure made of microwavetransparent, high-temperature stable ceramics (such as boron nitride andmullite), microwaves only heat the strong microwave absorbing(electrically conductive) semiconducting films, which present a very lowthermal mass in comparison with a conventional furnace where thesurroundings of the sample are also heated. Thus, heating rates>600°C./s are possible.

Microwave heating has an advantage of selective heating. When microwavepower radiates on two different materials, such as a highly doped SiCwafer (which tends to be a strong microwave absorber), and asemi-insulating SiC wafer (which tens to be a poor microwave absorber),microwaves may selectively heat up highly doped SiC of the strongmicrowave absorber while leaving a negligible direct, heating effect onthe semi-insulating SiC.

II. GROWING SiC NANOWIRES BY A MICROWAVE BASED SUBLIMIATION—SANDWICHMETHOD

-   -   A. Introduction

A new method for the growth of SiC nanowires by a novelcatalyst-assisted sublimation-sandwich (SS) method was developed. It isa simple and effective approach to grow SiC nanowires by combining theadvantages of physical vapor transport (PVT) process and catalyticvapor-liquid-solid (VLS) growth mechanism. As one exemplary embodiment,for heating, an ultra-fast microwave heating technique developed by LTtechnologies is employed. Different morphologies of 1-D SiCnanostructures may be grown by appropriately adjusting the processparameters. The as-grown nanowires were characterized using FESEM,energy dispersive x-ray spectroscopy (EDAX), electron backscattereddiffraction (EBSD), transmission electron microscopy (TEM), andmicro-Raman spectroscopy.

Novel features of this SS method include, but are not limited to, fastgrowth rate (1-2 μm/s), which is at least 1-3 orders of magnitude higherthan any existing method for growing SiC nanowires; potential control ofmorphology of SiC nanowires including shape, size, location andorientation; potential control of polytypes and doping concentration ofSiC nanowires; and high process yield and low cost.

-   -   B. Sublimation-Sandwich Method        -   1. Nanowire Growth Conditions

The following description pertains to exemplified embodiments offabricating SiC nanowires using the SS method. In no way does thepresent invention limits these teachings to SiC nanowires.

The key conditions for high-yield and cost effective fabrication ofnanowires (such SiC) are fast growth rate, and controlled shape andsize. While these conditions are necessary for SiC, these conditions mayalso apply to other types of nanowires.

TABLE 2 lists, step by step, all the conditions required to achieve afast process rate for each step in the sublimation sandwich growthprocess. It can be seen that two conditions are critical, namely: (1) ahigh substrate wafer temperature T2, and (2) a high temperature gradientΔT, with which a fast process rate can be achieved for each step in thesublimation sandwich process and consequently for the overall growthrate. The results from proof-of-concept experiments confirmed that avery high growth rate of 1-2 μm/s can be achieved at T2>1750° C. andΔT>100° C. This growth rate is about at least 10-100 times faster thanthose of the current conventional growth methods.

TABLE 2 Conditions Required for Achieving Fast Process Rate for EachStep in the SS Process Steps in SS process Conditions for fast processrate at each step 1 Sublimation of SiC from the Vapor phasestoichiometry by congruent source evaporation surface of the sourcewafer High T1 for high vapor pressure High ΔT (ΔT = T2 − T1) for fastvapor transport 2 Absorption of vapors by High T2 for supers aturationof metal-Si—C liquid alloy phase metal (e.g. Fe) catalyst resulted fromfast absorption of Si- and C-bearing vapor species by metal-catalyst 3Growth of SiC nanowires High T2 for fast diffusion of Si and C speciesin Fe(Si,C) from Fe(Si,C) liquid droplet liquid alloy followed byprecipitation of SiC nanostructures from this alloy

In addition to high growth rate, controlling the shape and size isanother key for high yield fabrication of nanowires with desiredfeatures. Different shapes of SiC nanowires that can be grown includenanocones, nanorods, and nanoneedles. It was observed from theexperiments that the two factors that control the shape of SiC nanowiresare the substrate wafer temperature T2 and the temperature gradient ΔT,as shown in TABLE 3.

TABLE 3 Factors to Control the Shape and Morphology of SiCNanostructures Control of the shape in growth of SiC SubstrateTemperature nanostructure wafer T2 gradient ΔT Selectivity Nanocones LowLow of Shape Nanorods Medium Medium Nanoneedles High High 2D and 3D Veryhigh Very high nanostructures

Similar results have been reported on CVD growth of SiC nanostructures,where the growth rate is used as one of the controlling factors insteadof the temperature gradient ΔT.

Nevertheless, both results are similar because the growth rate isdirectly proportional to the temperature gradient. It can be seen thatnanocones grow at low T2 and ΔT, nanorods at medium T2 and ΔT,nanoneedles at high T2 and ΔT, and 2D and 3D nanostructures at very highT2 and ΔT.

In addition to T2 and ΔT, fast heating and cooling rate are alsonecessary because nanowires of undesired shapes may form during rampingup and cooling stages due to the transient temperature variation if theheating and cooling is slow. However, the present invention's microwaveheating system has the capability of fast heating and cooling to keepthe ramping time short for eliminating the formation of undesiredshapes.

Growing different SiC polytypes require certain favorable conditions, asshown in TABLE 4.

TABLE 4 Conditions Favorable for Growth of Different SiC NanowirePolytypes 4H—SiC 6H—SiC 3C—SiC Substrate Temperature T2 High HigherRelative low Temperature gradient ΔT Low Low High Polarity of substrateSiC wafer C-face Si-Face Si-face Si/C molar ratio in ambient C-richSi-rich Excess Si-rich Presence of certain impurities/ N, Ge, Sn dopingPolytypes of SiC substrate wafer Independent

Overall, with respect to substrate temperature, the 4H—SiC and 6H—SiCpolytypes are thermodynamically more stable than the metastable 3C—SiCpolytype. The formation of hexagonal 4H- and 6H—SiC requires highersubstrate temperature than that of 3C—SiC. The 3C—SiC is thermallyunstable and may transform to more stable polytypes of 4H- and 6H—SiC athigh temperature. However, the metastale 3C—SiC is the stable structurein nucleation stage and is always the first polytype that nucleates andoccurs during growth at low temperatures below 1600° C. in accordancewith the Ostwald step rule. Under non-equilibrium growth condition,where rearrangement of equilibrium growth is not possible, 3C—SiC isexpected to be the final polytype even for growth at a high temperature(e.g. >2000° C.).

As for temperature gradient, high temperature gradient will lead tofast, non-equilibrium growth, which is in favor of 3C—SiC growth. On thecontrary, low temperature gradient is in favor of 4H- and 6H—SiC growth.

Polarity of the substrate wafer is another factor to consider. The Cface of the SiC substrate wafer is in favor of 4H—SiC growth, whereasthe Si-face of the SiC substrate wafer is in favor of 3C—SiC and 6H—SiCgrowth.

For Si/C molar ratio in ambient (vapor phase stoichiometry), C-richcondition is in favor of 4H—SiC growth. Si-rich condition is in favor of6H—SiC growth. Excess Si-rich condition is in favor of 3C—SiC growth.

With respect to impurities and doping, it is known that nitrogen dopingmay enhance the formation and stability of 4H—SiC polytype. The presenceof certain impurities in the vapor phase (e.g., Ge, Sn, Pb, etc.) may bein favor of 4H—SiC growth.

In summary, the important operational parameters and functions requiredfor the SSM prototype unit include: (1) high ΔT (>100° C.) and high T2(>1750° C.) for fast growth rate, where high T2 is also in favor of 4H-and 6H—SiC polytypes; (2) controllable T1, T2 and ΔT for selectivegrowth of different shapes and polytypes; (3) controllable vaporcomposition of the surrounding environment for selective growth of aspecific SiC polytype, and for doping with desirable impurities; and (4)fast heating and cooling.

To achieve these parameters and functions, and to perform the SS method,the SSM heating system that was primarily designed for post-implantationannealing of ion-implanted SiC needs to be modified.

Modifications include, but are not limited to, introducing two opticaltemperature sensors to measure temperatures of both the source wafer andthe substrate wafer; redesigning the wafer holder; designing a movingstage and other fixtures to facilitate the control of the gap (d)between the source and substrate wafers; and stabilizing ΔT. Inaddition, a new environmental chamber will also be designed with a morecompact size and better control of mass flow and pressure of theexternal vapor sources, which may play an important role in manipulatingthe composition, doping level and SiC polytype of the nanowires. Toevaluate the modified unit and to determine the fundamental operationalparameters, operational tests can be carried out. Furthermore,controlling features, such as a microcontroller (e.g., FPGM), may beadded.

FIG. 5 shows a schematic of a typical “sandwich” cell employed in thepresent invention for SiC nanowire growth. The “sandwich cell” comprisestwo parallel 4H—SiC wafers with a very small gap, “d”, between them. Thebottom wafer is semi-insulating SiC, which will be referred to as the“substrate wafer” hereafter. The inner surface of the substrate wafer iscoated with a 5 nm layer of Fe, Ni, Pd, or Pt that acts as a catalystfor the VLS growth of SiC nanowires. The top wafer is a heavily n-type(nitrogen doped) in-situ doped SiC, which will be referred to as the“source wafer”. As further illustrated, the microwave heating head isplaced around the sandwich cell. Due to the difference in electricalconductivity of the source wafer and the substrate wafer, at a givenmicrowave power, the source wafer temperature is higher than thesubstrate wafer temperature, resulting in a temperature gradient, ΔTbetween the two wafers. When the Si- and C-containing species, such asSi, SiC₂, and Si₂C, sublimate from the source wafer attemperatures>1500° C., the temperature gradient ΔT provides the drivingforce for transporting these species to the substrate wafer. On thesubstrate wafer surface, the metal film is either already molten at thegrowth temperature, or it melts after absorbing the Si species and formsspherical islands to minimize its surface free energy. The Si- andC-containing vapor species are absorbed by these metal islands,converting them into liquid droplets of metal-Si—C alloys. Once thisalloy reaches a saturation point for SiC, a precipitation of SiC occursat the liquid-substrate interface thereby leading to a VLS growth of theSiC nanowires. The nanowires always terminate in hemispherical metal-Sialloy end-caps. While Group VIII metals facilitated growth of SiCnanowires, Au was unsuccessful as a catalyst in this VLS process. Notraces of Au on the sample surface were found during a post-growthSEM/EDAX inspection, due to its possible evaporation at the growthtemperature. The only results presented are those obtained using Fe as ametal catalyst since SiC growth using other Group VIII metals producedsimilar results.

-   -   2. Unique Features

The present invention's SS method can reliably grow SiC nanostructureswith predictable morphologies and very high growth rates. As a result,there exists a vast body of information available for controlling thepolytype, doping, orientation, etc. of the SiC growth. The sandwich cellused in this work is a nearly closed system because of the small gapbetween the source and substrates wafers, which allows precise controlof the composition of the vapor phase in the growth cell. At the sametime the system is open to the species exchange between the sandwichgrowth cell and the surrounding environment in the chamber. Byappropriately adjusting the composition of the precursor species in thevapor, this approach has the potential to control the doping levels, orcreate heterostructures in the growing nanostructures. Another importantfeature of the sandwich growth cell is its compact size, whichsignificantly reduces the volume of the surrounding chamber. The use ofa small chamber not only saves the cost by utilization of small amountof expensive source materials, but also significantly reduces the vacuumpumping cycle time, which is needed for a high throughput fabrication.Yet another novel feature is the dynamic range of temperature rampingrates (≧600° C./s) that are possible using the microwave heating system.This is another process parameter which can be tweaked to circumventsome thermodynamic restrictions.

-   -   3. Experimental Parameters for SiC Nanostructure Growth

The substrate wafer temperature window for growing SiC nanostructures is1250° C. to 1750° C. In this embodied experimental growth process, theprecursor Si and C containing species sublimate from the source wafer.Significant sublimation of Si and C species from a SiC wafer requirestemperatures>1400° C. (at 1 atm pressure). Therefore, the growthtemperatures used are higher than those typically employed for SiCnanowire growth (1000° C.-1200° C.), since the previous works did notemploy sublimated Si and C containing species from a SiC wafer as thesource material.

The growth is performed for time durations of 15 s to 40 s. The ΔTbetween the source wafer and the substrate wafer is varied from 150° C.to 250° C. by varying the spacing (d) from 300 μm to 600 μm. All thegrowth experiments are performed in an atmosphere of UHP-grade nitrogen.Growth was also attempted in other inert gases, such as Ar, He, and Xe.But they were found to ionize due to the intense microwave field in thegrowth chamber.

-   -   4. Experimental Apparatus for Characterizing SiC Nanostructures

A Hitachi S-4700 FESEM was used for studying the surface morphology ofthe SiC nanowires. An EDAX attachment to the S-4700 microscope was usedto determine chemical composition, and a HKL Nordlys II EBSD detectorattached to the S-4700 microscope was used to collect the EBSD patterns.X-ray diffraction was performed using a Bruker D8 x-ray diffractometerequipped with an area detector. Samples for TEM were prepared bydispersing nanowires on lacey carbon-coated copper grids. The sampleswere examined in a Philips CM-30 TEM operated at 200 kV. Samples forμ-Raman spectroscopy were prepared by dispersing the SiC nanowires on ana-plane sapphire substrate. Raman spectra were obtained with 514.5 nmexcitation (argon ion laser) in a back-scattering configuration using acustom-built Raman microprobe system. Incident laser radiation wasdelivered to the microprobe using a single mode optical fiber, resultingin a depolarized radiation exiting the fiber (no subsequent attempt wasmade to polarize the radiation). Radiation was introduced into themicroscope optical path using an angled dielectric edge filter in theso-called injection-rejection configuration. Collected scatteredradiation was delivered to a 0.5 m focal length imaging singlespectrograph using a multimode optical fiber. A 100× infinity-correctedmicroscope objective was used for focusing incident radiation andcollecting scattered radiation. Power levels at the sample were lessthan 1.6 mW. Light was detected with a back-illuminated, charge coupleddevice camera system operating at −90° C. The instrumental bandpass(FWHM) was approximately 3.1 cm⁻¹.

-   -   5. Morphology and Chemical Composition of SiC Nanowires

Growth of SiC nanowires was observed over a very narrow range of bothsubstrate temperature ‘T_(s)’ (1650° C.-1750° C.) and ΔT (≈150° C.).FIG. 6 shows a plan-view FESEM image of the nanowires grown at 1700° C.for 40 s. The growth and structural characterization of these nanowires,which are 10 μm to 30 μm long, is the main focus of this exemplifiedembodiment. Typical 3C—SiC nanowire lengths reported in the literaturerange from as short as 1 μm to as long as several mm. The diameters ofthe nanowires grown here are in the range of 15 nm to 300 nm. EDAXanalysis of the nanowires (not shown) indicates that they mainly consistof Si and C with traces of nitrogen. The likely source of this nitrogenis the ambient atmosphere. However, the source wafer is also doped withnitrogen (ND=1×1019 cm⁻³). The exact mechanism of the accommodation ofnitrogen in SiC nanowires requires further investigation. EDAX spectra(not shown) from the droplets at the nanowire tips consist of thecorresponding metal and Si.

The statistical distribution of the nanowire diameters was determinedusing FESEM images of nanowire samples dispersed on a low-resistivity Siwafer. The diameters of 50 nanowires were measured at differentlocations on the wafer. As illustrated in FIG. 7, the diameterdistribution for the SiC nanowires grown at 1700° C. for 40 s revealsthat 42% of the nanowires exhibited diameters in the range of 15 nm to100 nm, while 14% of nanowires had diameters in excess of 300 nm.

In addition to SiC nanowires, growth of cone-shaped and needle-shapedSiC nanostructures was also observed under different growth conditions.For ΔT=150° C., the substrate wafer temperatures in the range of 1250°C. to 1650° C. for 15 s to 1 min durations yielded mainly cone-shapedquasi 1-D SiC nanostructures, as shown in part (a) of FIG. 8. Suchnanostructures are 2 μm-5 μm long. Yet, substrate wafertemperatures>1750° C. for the same durations resulted in micron-sizedSiC deposits (not shown). In part (a) of FIG. 8, the “nanocones” taperoff along their axis from thick catalytic metal tips. This suggests thatthe diameter of the droplets increased during the growth of the cones.The diameters of their thin ends are about 10 nm to 30 nm, while thebroad portion at the top just under the catalytic metal tips, range from100 nm to 200 nm. The fact that the diameter of the cones increases withgrowth duration must mean that there is an Oswald ripening effect (i.e.,the metal is transferred from the smaller diameter droplets to thelarger diameter ones, possibly via surface diffusion). The short lengthof the cones results from a relatively low SiC growth rate for theexperimental conditions under which the cones are grown. Thus, thesurface diffusion length for the liquid metal to flow from the smallerdiameter droplets to the larger diameter droplets is short.

As shown in part (b) of FIG. 8, increasing the ΔT to 250° C. (byincreasing ‘d’ from 300 μm to 600 μm) at a T_(s) of 1700° C. resulted inmainly needle-shaped SiC nanostructures, which are 50 μm-100 μm inlength. These needles are narrow under the catalytic metal tips. It isobvious that the diameter of the metal droplets catalyzing the needlegrowth decreases with growth duration. Because the source wafertemperature for needle growth (1900° C.-2000° C.) is the highest amongthe temperatures explored in this exemplified embodiment, it is possiblethat the metal droplets evaporate during crystal growth due to hightemperatures in the vicinity of the droplets. The much longer needles(in comparison with the cones) also result in a greater surfacediffusion length for the liquid metal to flow between droplets, whichmight have inhibited significant surface diffusion of the metal.

-   -   6. Crystallography of SiC Nanowires

FIG. 9 shows a typical θ-2θ powder x-ray diffraction spectrum obtainedfrom the SiC nanowires. The only phase unambiguously identified from theXRD spectrum is 3C—SiC.

FIG. 10 shows three parts. Part (a) shows an FESEM image of a SiCnanowire harvested on a heavily doped Si substrate. Parts (b) and (c)respectively show EBSD patterns from the SiC nanowire and catalytic cap.The EBSD pattern from the nanowire was successfully indexed to 3C SiCand not one of the hexagonal variants (2H, 4H, etc.) or rhombohedralvariants (e.g. 15R). This distinction relies on the presence and/orabsence of relatively weak lines in the EBSD spectra, but the result wasunequivocal. The growth direction of the nanowire was identified as

112

, which is in contrast to the

111

growth direction commonly observed for 3C SiC nanowires. The EBSDpattern from the catalytic tip of the SiC nanowire, which clearly showsthe six-fold symmetry about the c-axis, was indexed according to thehexagonal Fe₂Si phase. One of the reasons as to why the

112

growth direction is preferred for the SiC nanowires grown in this workover the commonly reported

111

direction could be the very high temperatures (1650° C.-1750° C.) usedin this work for nanowire growth. The nanowire growth generally occursalong the direction, whose corresponding face has the highest surfaceenergy, so that that particular face is not exposed. The {111} being athree cluster face must have a higher surface energy for SiC at lowertemperatures, thereby driving the nanowire growth along the

111

direction. At higher temperatures, the nucleation rate along directionsnormal to lower atomic density planes such as {110} and {112} is knownto be faster than {111}. It has been observed that 3C—SiC nanowiregrowth direction switched from

111

to

110

, when the growth temperature was increased beyond 1500° C.

The occurrence of different polytypes dependent on the temperature hasbeen studied in sublimation experiments under near-equilibriumconditions. Factors affecting the crystal polytype are the temperatureand the pressure in the growth chamber, the polarity of the seedcrystal, the presence of certain impurities and the Si/C ratio. Undermore Si-rich (or C-rich) conditions the formation of the cubic (orhexagonal) polytype should be preferred. Nucleation far from equilibriumconditions and a nitrogen atmosphere has been generally assumed tostabilize the cubic polytype. This effect is supported by nucleationtheory. Furthermore, 3C SiC has the lowest surface energy among allpolytypes. Since, in the experiments, Si- rich precursor species arepresent (Si, Si₂C), and nucleation occurs far from equilibriumconditions in a nitrogen atmosphere, the growth of 3C—SiC is to beexpected from the above considerations. Furthermore, because nanowireshave a large surface to volume ratio, the low surface energy of the3C—SiC polytype makes it much more favorable to grow 3C—SiC over otherpolytypes.

As mentioned before, SiC nanowire growth was successfully performed byusing other Group VIII metal catalysts (such as Ni, Pd, and Pt) inaddition to Fe. In each case, the EBSD patterns from the nanowires wereindexed to 3C—SiC and the growth direction of the nanowire wasidentified as parallel to the

112

crystallographic directions, which indicates the unique

112

growth direction observed for SiC nanowire growth in this work does notdepend on the metal catalyst used for the growth. EBSD patterns from theend-caps of the SiC nanowires grown using (a) Ni catalyst, (b) Pdcatalyst, and (c) Pt catalyst, may be taken. These catalysts wererespectively indexed to Ni₃Si, Pd₂Si, and PtSi phases.

It should be noted that a much higher density of nanowires in comparisonwith other 2-D deposits are observed for the growth performed using Fe,Ni, and Pd. It was still possible to grow SiC nanowires using Pt aswell. But the yield of the nanowires in comparison with other 2-Ddeposits was much lower. This lower yield can be possibly attributed tothe higher melting point of the Pt—Si alloys compared to other metalsused in these embodiments. However, no major difference in thestructural characteristics of the nanowires grown using the differentmetal catalysts were observed.

A representative <101> selected area electron diffraction pattern may berecorded from a single SiC nanowire, where the reflections are indexedaccording to the F-centered cubic 3C—SiC unit cell. The recording wereall consistent with a cubic 3C—SiC structure. The growth direction isparallel to

112

, as was inferred from the nanowire projections in several zone axisorientations, which is consistent with EBSD results.

FIG. 11 shows at-least two different types of SiC nanowires wereobserved under TEM. Also shown are diffraction contrast TEM imagesrepresentative of these two types of nanowires. The nanowire shown inpart (a) exhibits twinning on four non-equivalent {111} planes, with thegrowth direction switching among the

112

directions in these planes (≈70° apart), which creates an impression ofnanowire bending. The twinning was confirmed through the selected areaelectron diffraction patterns (not shown). The nanowire shown in part(b) is relatively straight but features a high-incidence of planar {111}defects (presumably, stacking faults and/or twins) parallel to thegrowth axis. These defects produced streaks of diffuse intensity alongthe <111> direction in electron diffraction patterns. It should be notedthat even though an image of a thin (50 nm diameter) straight nanowireand a thick (500 nm diameter) bent nanowire are illustrated, thenanowire diameter has no bearing on whether a nanowire is straight orbent. Thick, straight nanowires and thin bent nanowires have also beenobserved.

-   -   7. Raman Study of SiC Nanowires

FIG. 12 shows a typical micro-Raman spectrum obtained from an isolatedSiC nanowire. The most intense feature is observed at ≈800 cm⁻¹ and isattributed to zone center transverse optical (TO) phonon modes in3C—SiC. This feature is composed of at least two peaks with centerwavenumbers of ≈794 cm⁻¹ and ≈810 cm⁻¹ (obtained by performing a peakdeconvolution assuming only two peaks) and exhibits a shoulder at ≈756cm⁻¹. In comparison, bulk 3C—SiC Raman spectra exhibit only one TO modeat ≈796 cm⁻¹. The TO phonon mode at 794 cm⁻¹ in the nanowire spectrum iscomparable with bulk 3C—SiC. However, the appearance of a second TOphonon mode at 810 cm⁻¹ in the nanowire spectrum indicates that thereare regions in the nanowire under compressive strain. A relatively largeincrease in the SiC TO phonon wavenumber (≈5 cm⁻¹ to ≈6 cm⁻¹) has beenreported in 3C—Sic grown on TiC and attributed to compressive strain inthe SiC layer. A likely cause of the strain is the presence of planardefects in the nanowires, as identified by TEM. It is possible thateither the low-strain region grows with a lower defect concentrationthan the high-strain region or that the defect concentration is highenough to lead to strain relaxation in the low-strain region.

Broader, weaker features observed at ≈480 cm⁻¹ to ≈640 cm⁻¹ and ≈820cm⁻¹ to ≈980 cm⁻¹ are attributed to scattering by phonon modesoriginating from other than the Brillouin zone center. In pure, perfectcrystals, only zone center optical phonon modes should be allowed forthe scattering conditions employed in these embodiments. However, thisrestriction can be relaxed due to the presence of defects which destroytranslational symmetry. The resulting Raman spectrum exhibits featuresof the phonon density of states rather than only zone center phononmodes. Hence, the ≈480 cm⁻¹ to ≈640 cm⁻, ≈820 cm⁻¹ to ≈980 cm⁻¹, and≈756 cm⁻¹ features are attributed to defect-induced acoustic (transverseand longitudinal) phonon mode scattering, LO phonon mode scattering, andTO phonon mode scattering, respectively, from throughout the Brillouinzone. Surface optical phonon modes may also contribute to the signalobserved in ≈900 cm⁻¹ to ≈980 cm⁻¹ range. No longitudinal optical (LO)phonon modes are observed. This lacking is consistent with previouslyreported SiC nanowire spectra obtained in this geometry.

-   -   C. Summary

In summary, a novel technique for the controlled rapid growth of 1-Dnanostructures of 3C—SiC using various Group VIII transition metalcatalysts has been developed. The experimental parameters that dictatethe growth of faceted nanowires (with straight sidewalls), nanoneedlesand nanocones (with tapering sidewalls) have been identified. Thenanowires are found to grow by the VLS mechanism at substratetemperatures in the range of 1650° C.-1750° C., for growth durations of15 s-40 s, along the

112

crystallographic directions. TEM studies have indicated the presence oftwo types of nanowires, one type maintains a constant growth direction,and another type frequently changes its growth direction by twinning.Also, several stacking faults running along the length of the nanowireshave been identified. Micro-Raman spectra of the SiC nanowires, inaddition to confirming the 3C-polytype, also indicate the presence ofregions exhibiting different compressive strain in the nanowire as wellas non Brillouin zone-center modes.

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IV. STATEMENTS

While various embodiments have been described above, it should beunderstood that they have been presented by way of example, and notlimitation. It will be apparent to persons skilled in the relevantart(s) that various changes in form and detail can be made thereinwithout departing from the spirit and scope. In fact, after reading theabove description, it will be apparent to one skilled in the relevantart(s) how to implement alternative embodiments. Thus, the presentembodiments should not be limited by any of the above describedexemplary embodiments.

In addition, it should be understood that any figures which highlightthe functionality and advantages, are presented for example purposesonly. The disclosed architecture is sufficiently flexible andconfigurable, such that it may be utilized in ways other than thatshown. For example, the steps listed in any flowchart may be re-orderedor only optionally used in some embodiments.

Further, the purpose of the Abstract of the Disclosure is to enable theU.S. Patent and Trademark Office and the public generally, andespecially the scientists, engineers and practitioners in the art whoare not familiar with patent or legal terms or phraseology, to determinequickly from a cursory inspection the nature and essence of thetechnical disclosure of the application. The Abstract of the Disclosureis not intended to be limiting as to the scope in any way.

Finally, it is the applicant's intent that only claims that include theexpress language “means for” or “step for” be interpreted under 35U.S.C. 112, paragraph 6. Claims that do not expressly include the phrase“means for” or “step for” are not to be interpreted under 35 U.S.C. 112,paragraph 6.

1. A microwave-based sublimation-sandwich silicon carbide (SiC) polytypegrowth method comprising: a. creating a sandwich cell by placing asource wafer parallel to a substrate wafer, leaving a small gap betweenthe source wafer and the substrate wafer; b. placing a microwave heatinghead around the sandwich cell to selectively heat the source wafer to asource wafer temperature and the substrate wafer to a substrate wafertemperature; c. creating a temperature gradient between the source wafertemperature and the substrate wafer temperature; d. sublimating silicon(Si-) and carbon (C-) containing species from the source wafer,producing Si- and C-containing vapor species; e. converting the Si- andC-containing vapor species into liquid droplets of metal-ion alloys byallowing the substrate wafer to absorb the Si- and C-containing vaporspecies; and f. growing nanostructures on the substrate wafer once thealloys reach a saturation point for SiC.
 2. The method according toclaim 1, wherein the SiC polytype is a hexagonal SiC or cubic SiC. 3.The method according to claim 1, wherein the source wafer is an n-typeor p-type doped SiC.
 4. The method according to claim 1, wherein thesubstrate wafer is a semi-insulating SiC or at least one order lessdoped SiC compared to the source wafer.
 5. The method according to claim1, wherein the small gap is at least about 0.3 mm.
 6. The methodaccording to claim 1, wherein the inner surface of the substrate waferis coated with a catalyst, creating a catalyst layer.
 7. The methodaccording to claim 6, wherein the catalyst layer is a patterned layer.8. The method according to claim 1, wherein the sandwich cell and themicrowave heating head are in a vacuum chamber or in a dopant gasatmosphere.
 9. The method according to claim 1, wherein the substratewafer temperature is greater than or about equal to the melting point ofthe catalyst, and the temperature gradient is at least about 100° C. 10.The method according to claim 1, wherein a heating rate is at leastabout 100° C./s and a cooling rate is at least about 100° C./s.
 11. Themethod according to claim 1, further including controlling themorphology of the nanostructures by varying the substrate wafertemperature and the temperature gradient.
 12. The method according toclaim 1, further including controlling the SiC polytype growth byvarying the substrate wafer temperature and polarity of the substratewafer.
 13. The method according to claim 12, wherein the polarity isSi-face or C-face.
 14. The method according to claim 1, furtherincluding controlling the SiC polytype growth by varying vapor phasecomposition.
 15. The method according to claim 14, wherein the vaporphase composition includes an Si/C molar ratio in ambient andimpurities.
 16. The method according to claim 1, further includingcontrolling the morphology of the nanostructures by selecting a sourcewafer with at least one dopant.
 17. The method according to claim 16,wherein the dopant is aluminum, nitrogen, or a combination thereof. 18.A sublimation-sandwich silicon carbide (SiC) polytype growth methodcomprising: a. creating a sandwich cell by placing a source waferparallel to a substrate wafer, leaving a small gap between the sourcewafer and the substrate wafer; b. placing a heating unit around thesandwich cell to selectively heat the source wafer to a source wafertemperature and the substrate wafer to a substrate wafer temperature; c.creating a temperature gradient between the source wafer temperature andthe substrate wafer temperature; d. sublimating silicon (Si-) and carbon(C-) containing species from the source wafer, producing Si- andC-containing vapor species; e. converting the Si- and C-containing vaporspecies into liquid droplets of metal-ion alloys by allowing thesubstrate wafer to absorb the Si- and C-containing vapor species; and f.growing nanostructures on the substrate wafer once the alloys reach asaturation point for SiC.
 19. The method according to claim 18, whereinthe SiC polytype is a hexagonal SiC or cubic SiC.
 20. The methodaccording to claim 18, wherein the inner surface of the substrate waferis coated with a catalyst, creating a catalyst layer.